There is known a technique for increasing processing speed of a microprocessor, which is called a pipeline processing. In the pipeline processing, instructions to be processed by a processor core is divided into stages, such as instruction fetch, instruction decode, and instruction execute, and the processes in the respective stages are performed in parallel.
In order to efficiently perform the pipeline processing, it is necessary that the processing times in the respective stages should be equal. For this purpose, an instruction cache, in which time required for memory access is short, is disposed, so as to increase the speed of the instruction fetch. An example of such technique is disclosed in JP-A-2003-162446.
In the conventional microprocessor, it is unable to determine the type of the instruction, unless the instruction is decoded. Accordingly, even when the instruction is an instruction for which no processing is required, such as a NOP (No OPeration) instruction, the operation of the instruction fetch and the instruction decode are inevitably performed. As a result, electric power is wastefully consumed in the stages of the instruction fetch and the instruction decode for the NOP instruction.
Such wasteful power consumption due to execution of a NOP instruction is sometimes noticeably increased particularly in a microprocessor of a VLIW (Very Long Instruction Word) type because of the following reason. In a microprocessor of the VLIW type, plural instructions are collected into one instruction, and executed as single instruction. In a case where the number of instructions to be simultaneously executed does not reach a specified number, the deficiency is therefore filled with NOP instructions. Accordingly the appearance frequency of NOP instructions is considerably high in the microprocessor of the VLIW type.
In a case where the instruction to be processed is an unconditional branch instruction, the next instruction that is read from the instruction cache will be invalid. However, in the pipeline processing, while the unconditional branch instruction is being decoded, the instruction fetch for the next instruction is already been started. Accordingly, also in this case, electric power is wastefully consumed for the operation in the instruction fetch stage and the access to the instruction cache.
As described above, in a conventional microprocessor, there is a problem in that the electric power is wastefully consumed depending on the type of an instruction.